This invention relates generally to semiconductor integrated circuit devices and more particularly, it relates to a CMOS incrementer cell which is operable at high speeds. A number of incrementer cells of the present invention may be connected together to implement a four-bit incrementer, a twelve-bit incrementer and the like without decreasing significantly the operational speed thereof.
There are known in the prior art a number of incrementer circuits, but they tend to suffer from the disadvantage in that as the number of bits to increment is increased the operational speed is slowed down significantly. Further, these prior incrementers tend to be formed of irregular structures which increase substantially the cost in design layout and manufacturing. Moreover, these conventional incrementer circuits are complex and thus require the use of increased amounts of chip area, thereby adding to the expense of production.
It would therefore be desirable to provide a CMOS incrementer cell in which a number of them could be connected together to form an N-bit incrementer so that the operational speed thereof is not significantly reduced as the number of bits is increased. Further, it would be expedient to construct the incrementer cell to be of a regular structure so as to conform to a repeatable pattern suitable for very large scale integration (VSLI) with high packing density.